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Title: Design, Simulation, Synthesis and Implementation of Wallace Tree Multiplier
Authors: Girma, Taye
Keywords: Wallace tree multiplier, carry lookahead adders, and multiplier delay
Issue Date: 2009
Abstract: This paper deals with design, synthesis, simulation and implementation of 8x8 Wallace Tree Multiplier. Multipliers form the heart of any DSP operation and determine the performance of general-purpose microprocessors. Wallace tree is an efficient hardware implementation of a circuit that multiplies two integers. It consists of three stages. In the first stage, the partial product matrix is formed or generated. This is to mean multiplying (ANDing) each bit of one of the arguments called multiplier, by each bit of the other arguments called multiplicand. Depending on position of the multiplied bits, the wires carry different weights. Reduce the number of partial products to two by layers of full and half adders. Group the wires in two numbers, and add them with a conventional adder. In the second stage, this partial product matrix is reduced to a height of two through taking any three wires with the same weights and input them into a full adder. In the final stage, these two rows are combined using a carry look ahead adder. Here, if there are two wires of the same weight left, input them into a half adder or if there is just one wire left, connect it to the next layer. The work results in reduction of number of gates that would be used in the design which in turn results in reduction of cost and delay.
Appears in Collections:The 1st Multidisciplinary Research Seminar

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